1. Technical Field
The present invention relates to a method and apparatus for characterizing integrated-circuits (ICs) in general, and in particular to a method and apparatus for characterizing IC interconnects. Still more particularly, the present invention relates to a method and apparatus for characterizing dimensions and parasitic capacitance between IC interconnects.
2. Description of the Prior Art
During the course of designing a very large-scale integrated (VLSI) circuit, it is desirable to render some form of circuit characterization in order to determine the performance of the circuit. The characteristic of a VLSI circuit is generally dependent upon two major factors, namely, parasitic capacitance and parasitic resistance.
For a VLSI circuit, signal delays are generally the sum of device (such as transistor) delays and wire delays. Wire delays are typically attributed by the parasitic capacitance associated with the interconnect materials within the VLSI circuit. Accordingly, it is important that the characteristics of the interconnect parasitic capacitances be well understood and controlled. Along the same vein, it is imperative to characterize all interconnect parasitic capacitances within a VLSI circuit in order to determine whether or not they exceed certain design criteria.
Interconnect parasitic capacitance characterization may be performed before and after the actual fabrication of a VLSI circuit. Before fabrication, characterization is performed via device modelling and circuit simulations. After the VLSI circuit has been fabricated, characterization may be performed by direct measurement. In practice, however, interconnect characterization via direct measurement is very difficult because the magnitude of the parasitic quantities, such as resistance, capacitance and inductance, is very small. Consequently, it would be desirable to provide an improved method and system for characterizing dimensions as well as parasitic capacitance between IC interconnects without utilizing direct measurement.